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19-2530; Rev 1; 1/03
P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay
General Description
The MAX6746-MAX6753 low-power microprocessor (P) supervisory circuits monitor single/dual system supply voltages from 1.575V to 5V and provide maximum adjustability for reset and watchdog functions. These devices assert a reset signal whenever the VCC supply voltage or RESET IN falls below its reset threshold or when manual reset is pulled low. The reset output remains asserted for the reset timeout period after VCC and RESET IN rise above the reset threshold. The reset function features immunity to power-supply transients. The MAX6746-MAX6753 have 2% factory-trimmed reset threshold voltages in approximately 100mV increments from 1.575V to 5.0V and/or adjustable reset threshold voltages using external resistors. The reset and watchdog delays are adjustable with external capacitors. The MAX6746-MAX6751 contain a watchdog select input that extends the watchdog timeout period by 128x. The MAX6752/MAX6753 contain a window watchdog timer that looks for activity outside an expected window of operation. The MAX6746-MAX6753 are available with a push-pull or open-drain active-low RESET output. The MAX6746- MAX6753 are available in an 8-pin SOT23 package and are fully specified over the automotive temperature range (-40C to +125C).
Features
o Factory-Set Reset Threshold Options from 1.575V to 5V in ~100mV Increments o Adjustable Reset Threshold Options o Single/Dual Voltage Monitoring o Capacitor-Adjustable Reset Timeout o Capacitor-Adjustable Watchdog Timeout o Min/Max (Windowed) Watchdog Option o Manual Reset Input Option o Guaranteed RESET Valid for VCC 1V o 3.7A Supply Current o Push-Pull or Open-Drain RESET Output Options o Power-Supply Transient Immunity o Small 8-Pin SOT23 Packages
MAX6746-MAX6753
Ordering Information
PART MAX6746KA_ _-T MAX6747KA_ _-T MAX6748KA-T MAX6749KA-T MAX6750KA_ _-T MAX6751KA_ _-T MAX6752KA_ _-T MAX6753KA_ _-T TEMP RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C PIN-PACKAGE 8 SOT23-8 8 SOT23-8 8 SOT23-8 8 SOT23-8 8 SOT23-8 8 SOT23-8 8 SOT23-8 8 SOT23-8
Applications
Medical Equipment Automotive Intelligent Instruments Portable Equipment Battery-Powered Computers/Controllers Embedded Controllers Critical P Monitoring Set-Top Boxes Computers
Pin Configurations
TOP VIEW
RESET IN (MR) 1 SWT 2 SRT 3 8 7 VCC RESET WDI WDS
Note: "_ _" represents the two number suffix needed when ordering the reset threshold voltage value for the MAX6746/MAX6747 and MAX6750-MAX6753. The reset threshold voltages are available in approximately 100mV increments. Table 2 contains the suffix and reset factory-trimmed voltages. All devices are available in tape-and-reel only. There is a 2500-piece minimum order increment for standard versions (see Table 3). Sample stock is typically held on standard versions only. Nonstandard versions require a minimum order increment of 10,000 pieces. Contact factory for availability.
MAX6746- MAX6751
6 5
GND 4
Selector Guide appears at end of data sheet. Typical Operating Circuit appears at end of data sheet.
SOT23-8
( ) ARE FOR MAX6746 AND MAX6747 ONLY.
Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746-MAX6753
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +6.0V SRT, SWT, SET0, SET1, RESET IN, WDS, MR, WDI, to GND ..........................................-0.3V to (VCC + 0.3V) RESET (Push-Pull) to GND.........................-0.3V to (VCC + 0.3V) RESET (Open Drain) to GND ................................-0.3V to +6.0V Input Current (All Pins) .....................................................20mA Output Current (RESET) ...................................................20mA Continuous Power Dissipation (TA = +70C) 8-Pin SOT23 (derate 8.9mW/C above +70C)............714mW Operating Temperature Range .........................-40C to +125C Storage Temperature Range ............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +1.2V to +5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA = +25C.) (Note 1)
PARAMETER Supply Voltage SYMBOL VCC CONDITIONS TA = 0C to +125C TA = -40C to 0C VCC 5.5V Supply Current ICC VCC 3.3V VCC 2.0V VCC Reset Threshold Hysteresis VCC to Reset Delay Reset Timeout Period SRT Ramp Current SRT Ramp Threshold Normal Watchdog Timeout Period (MAX6746-MAX6751) Extended Watchdog Timeout (MAX6746-MAX6751) Slow Watchdog Period (MAX6752/MAX6753) Fast Watchdog Timeout Period, SET Ratio = 8, (MAX6752/MAX6753) Fast Watchdog Timeout Period, SET Ratio = 16, (MAX6752/MAX6753) tRP IRAMP VRAMP tWD tWD tWD2 VTH VHYST VCC falling from VTH + 100mV to VTH 100mV at 1mV/s CSRT = 1500pF CSRT = 100pF VSRT = 0 to 1.23V; VCC = 1.6V to 5V VCC = 1.6V to 5V (VRAMP rising) CSWT = 1500pF CSWT = 100pF CSWT = 1500pF CSWT = 100pF CSWT = 1500pF CSWT = 100pF CSWT = 1500pF tWD1 CSWT = 100pF CSWT = 1500pF tWD1 CSWT = 100pF 4.05 45.53 8.09 60.71 75.89 ms 91.08 728.6 728.6 200 1.173 5.692 5.692 See VTH selection table TA = -40C to+125C VTH 2% 0.8 20 7.590 0.506 250 1.235 7.590 0.506 971.5 64.77 971.5 64.77 121.43 151.80 ms 1214.4 1214.4 300 1.297 9.487 9.487 MIN 1.0 1.2 5 4.2 3.7 TYP MAX 5.5 5.5 10 9 8 VTH + 2% V % s ms nA V ms ms ms A UNITS V
2
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P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.2V to +5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA = +25C.) (Note 1)
PARAMETER Fast Watchdog Timeout Period, SET Ratio = 64, (MAX6752/MAX6753) Fast Watchdog Minimum Period (MAX6752/MAX6753) SWT Ramp Current SWT Ramp Threshold RESET Output Voltage LOW Open-Drain, Push-Pull (Asserted) RESET Output Voltage HIGH, Push-Pull (Not Asserted) RESET Output Leakage Current, Open Drain IRAMP VRAMP VOL VSWT = 0 to 1.23V, VCC = 1.6V to 5V VCC = 1.6V to 5V (VRAMP rising) VCC 1.0V, ISINK = 50A VCC 2.7V, ISINK = 1.2mA VCC 4.5V, ISINK = 3.2mA VCC 1.8V, ISOURCE = 200A VOH VCC 2.25V, ISOURCE = 500A VCC 4.5V, ISOURCE = 800A ILKG VCC > VTH, reset not asserted, V RESET = 5.5V 0.8 x VCC 0.8 x VCC 0.8 x VCC 1.0 A V SYMBOL tWD1 CSWT = 100pF 2000 200 1.173 250 1.235 300 1.297 0.3 0.3 0.4 V 1.01 ns nA V CONDITIONS CSWT = 1500pF MIN 11.38 TYP 15.18 MAX 18.98 ms UNITS
MAX6746-MAX6753
DIGITAL INPUTS (MR, SET0, SET1, WDI, WDS) VIL Input Logic Levels VIH VIL VIH MR Minimum Pulse Width MR Glitch Rejection MR to RESET Delay MR Pullup Resistance WDI Minimum Pulse Width RESET IN RESET IN Threshold RESET IN Leakage Current RESET IN to RESET Delay VRESET IN IRESET IN RESET IN falling at 1mV/s TA = -40C to +125C 1.216 -50 1.235 1 20 1.254 +50 V nA s Pullup to VCC 12 300 VCC 4.0V VCC < 4.0V 0.7 x VCC 1 100 200 20 28 s ns ns k ns 0.8 2.4 0.3 x VCC V
Note 1: Production testing done at TA = +25C. Over temperature limits are guaranteed by design.
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P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746-MAX6753
Typical Operating Characteristics
(VCC = +5V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX6746 toc02 MAX6746 toc03
RESET TIMEOUT PERIOD vs. CSRT
MAX6746 toc01
WATCHDOG TIMEOUT PERIOD vs. CSWT
100,000 WATCHDOG TIMEOUT PERIOD (ms) 10,000 EXTENDED MODE 1000 100 10 1 0.1 NORMAL MODE MAX6746-MAX6751 6 5 SUPPLY CURRENT (A) 4 3 2 1 0 100 1000 CSWT (pF) 10,000 100,000 1 2
10,000
RESET TIMEOUT PERIOD (ms)
1000
100
10
1
0.1 100 1000 CSRT (pF) 10,000 100,000
3
4
5
6
SUPPLY VOLTAGE (V)
NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE
MAX6746 toc04
NORMALIZED WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE
1.15 NORMALIZED TIMEOUT PERIOD 1.10 1.05 1.00 0.95 0.90 0.85 0.80 CSWT = 100pF CSWT = 1500pF
MAX6746 toc05
MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE
150 TRANSIENT DURATION (s) 125 100 75 50 25 0 VTH = 2.92V 0 200 400 600 800 1000 RESET OCCURS ABOVE THE CURVE
MAX6746 toc06
1.20 NORMALIZED TIMEOUT PERIOD 1.15 1.10 CSRT = 100pF 1.05 1.00 0.95 0.90 -50 -25 0 25 50 75 100
1.20
175
CSRT = 1500pF
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
RESET THRESHOLD OVERDRIVE (mV)
SUPPLY CURRENT vs. TEMPERATURE
MAX6746 toc07
NORMALIZED RESET IN THRESHOLD VOLTAGE vs. TEMPERATURE
MAX6746 toc08
RESET IN THRESHOLD vs. SUPPLY VOLTAGE
MAX6746 toc08b
NORMALIZED RESET THRESHOLD VOLTAGE
6 5 SUPPLY CURRENT (A) 4 3 VCC = 3.3V 2 1 0 -50 -25 0 25 50 75 100 VCC = 1.8V VCC = 5V
1.010 1.008 1.006 1.004 1.002 1.000 0.998 0.996 0.994 0.992 0.990
VCC = 5V
1.240
RESET IN THRESHOLD (V) -50 -25 0 25 50 75 100 125
1.239
1.238
1.237
1.236
1.235 1 2 3 4 5 6 TEMPERATURE (C) SUPPLY VOLTAGE (V)
125
TEMPERATURE (C)
4
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P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay
Typical Operating Characteristics (continued)
(VCC = +5V, TA = +25C, unless otherwise noted.)
VCC TO RESET DELAY vs. TEMPERATURE (VCC FALLING)
MAX6746 toc09
MAX6746-MAX6753
RESET AND WATCHDOG TIMEOUT PERIOD vs. VCC
MAX6746 toc10
RESET AND WATCHING TIMEOUT PERIOD vs. VCC
CSWT = CSRT = 1500pF
MAX6746 toc11
27.0
VCC FALLING AT 1mV/s
0.60
CSWT = CSRT = 100pF
9.0 8.5 TIMEOUT PERIOD (ms)
VCC TO RESET DELAY (s)
26.6
0.56 TIMEOUT PERIOD (ms)
RESET 8.0 WATCHDOG 7.5 7.0 6.5 6.0
26.2
0.52
25.8
0.48
25.4
0.44
25.0 -50 -25 0 25 50 75 100 125 TEMPERATURE (C)
0.40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VCC (V)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VCC (V)
Pin Description
PIN MAX6746 MAX6747 1 MAX6748- MAX6751 -- MAX6752 MAX6753 -- NAME FUNCTION Manual Reset Input. Pull MR low to manually reset the device. Reset remains asserted for the reset timeout period after MR is released. Reset Input. High-impedance input to the adjustable reset comparator. Connect RESET IN to the center point of an external resistor-divider to set the threshold of the externally monitored voltage. Logic Input. SET0 selects watchdog window ratio or disables the watchdog timer. See Table 1. Watchdog Timeout Input. MAX6746-MAX6751: Connect a capacitor between SWT and ground to set the basic watchdog timeout period (tWD). Determine the period by the formula tWD = 5.06 x 106 x CSWT with tWD in seconds and CSWT in Farads. Extend the basic watchdog timeout period by using the WDS input. MAX6752/MAX6753: Connect a capacitor between SWT and ground to set the slow watchdog timeout period (tWD2). Determine the slow watchdog period by the formula: tWD2 = 0.65 x 109 x CSWT with tWD2 in seconds and CSWT in Farads. The fast watchdog timeout period is set by pinstrapping SET0 and SET1. See Table 1. Reset Timeout Input. Connect a capacitor from SRT to GND to select the reset timeout period. Determine the period as follows: tRP = 5.06 x 106 x CSRT with tRP in seconds and CSRT in Farads. Ground
MR
--
1
--
RESET IN
--
--
1
SET0
2
2
2
SWT
3 4
3 4
3 4
SRT GND
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P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746-MAX6753
Pin Description (continued)
PIN MAX6746 MAX6747 MAX6748- MAX6751 MAX6752 MAX6753 NAME FUNCTION
5
5
--
WDS
Watchdog Select Input. WDS selects the watchdog mode. Connect WDS to ground to select normal mode and the watchdog timeout period. Connect WDS to VCC to select extended mode, multiplying the basic timeout period by a factor of 128. A change in the state of WDS clears the watchdog timer. Logic Input. SET1 selects the watchdog window ratio or disables the watchdog timer. See Table 1. Watchdog Input. MAX6746-MAX6751: A falling transition must occur on WDI within the selected watchdog timeout period or a reset pulse occurs. The watchdog timer clears when a transition occurs on WDI or whenever RESET is asserted.
--
--
5
SET1
6
6
6
WDI MAX6752/MAX6753: WDI falling transitions within periods shorter than tWD1 or longer than tWD2 force RESET to assert low for the reset timeout period. The watchdog timer begins to count after RESET is deasserted. The watchdog timer clears when a valid transition occurs on WDI or whenever RESET is asserted. See the Watchdog Timer section. Push/Pull or Open-Drain Reset Output. RESET asserts whenever VCC or RESET IN drops below the selected reset threshold voltage (VTH or VRESET IN, respectively) or manual reset is pulled low. RESET remains low for the reset timeout period after all reset conditions are deasserted, and then goes high. The watchdog timer triggers a reset pulse (tRP) whenever a watchdog fault occurs. Supply Voltage. VCC is the power-supply input and the input for fixed threshold VCC monitor.
7
7
7
RESET
8
8
8
VCC
6
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P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746-MAX6753
tWD1 (MIN) tWD1 (MAX) tWD2 (MIN) tWD2 (MAX)
GUARANTEED TO ASSERT RESET
GUARANTEED TO GUARANTEED TO NOT ASSERT ASSERT RESET RESET *UNDETERMINED *UNDETERMINED
WDI CONDITION 1
FAST FAULT
WDI CONDITION 2
NORMAL OPERATION
WDI CONDITION 3 *UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION
SLOW FAULT
Figure 1. MAX6752/MAX6753 Detailed Watchdog Input Timing Relationship
Detailed Description
The MAX6746-MAX6753 assert a reset signal whenever the VCC supply voltage or RESET IN falls below its reset threshold. The reset output remains asserted for the reset timeout period after VCC and RESET IN rise above its respective reset threshold. A watchdog timer triggers a reset pulse whenever a watchdog fault occurs. The reset and watchdog delays are adjustable with external capacitors. The MAX6746-MAX6751 contain a watchdog select input that extends the watchdog timeout period to 128x. The MAX6752 and MAX6753 have a sophisticated watchdog timer that detects when the processor is running outside an expected window of operation. The watchdog signals a fault when the input pulses arrive too early (faster that the selected tWD1 timeout period) or too late (slower than the selected tWD2 timeout period) (see Figure 1).
RESET is guaranteed to be in the correct logic state for VCC greater than 1V. For applications requiring valid reset logic when VCC is less than 1V, see the section Ensuring a Valid RESET Output Down to VCC = 0V.
RESET IN Threshold
The MAX6748-MAX6751 monitor the voltage on RESET IN using an adjustable reset threshold (VRESET IN) set with an external resistor voltage-divider (Figure 2). Use the following formula to calculate the externally monitored voltage (VMON_TH): VMON_TH = VRESET IN x (R1 + R2) / R2
VMON_TH
R1 VCC
VCC
Reset Output
The reset output is typically connected to the reset input of a P. A P's reset input starts or restarts the P in a known state. The MAX6746-MAX6753 P supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power-down, and brownout conditions (see theTypical Operating Circuit). RESET changes from high to low whenever the monitored voltage, RESET IN and/or VCC drop below the reset threshold voltages. Once VRESET IN and/or VCC exceeds its respective reset threshold voltage(s), RESET remains low for the reset timeout period, then goes high.
R2
RESET IN
GND
MAX6748 MAX6749 MAX6750 MAX6751
VMON_TH = 1.235 x (R1 + R2) / R2
Figure 2. Calculating the Monitored Threshold Voltage (VMON_TH) 7
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P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746-MAX6753
VMON_TH
guarantee RESET IN threshold accuracy and timing performance. The MAX6748 and MAX6749 can be configured to monitor VCC voltage by connecting VCC to VMON_TH.
VCC VCC
R1
Dual-Voltage Monitoring (MAX6750/MAX6751)
The MAX6750 and MAX6751 contain both factorytrimmed threshold voltages and an adjustable reset threshold input, allowing the monitoring of two voltages, VCC and VMON_TH (see Figure 2). RESET is asserted when either of the voltages falls below it respective threshold voltages.
RESET IN
R2 GND
MAX6748 MAX6749 MAX6750 MAX6751
Manual Reset (MAX6746/MAX6747)
Many P-based products require manual reset capability, to allow an operator or external logic circuitry to initiate a reset. The manual reset input (MR) can connect directly to a switch without an external pullup resistor or debouncing network. MR is internally pulled up to VCC and, therefore, can be left unconnected if unused. MR is designed to reject fast, falling transients (typically 100ns pulses) and it must be held low for a minimum of 1s to assert the reset output. A 0.1F capacitor from MR to ground provides additional noise immunity. After MR transitions from low to high, reset remains asserted for the duration of the reset timeout period. A manual reset option can easily be implemented with the MAX6748-MAX6751 by connecting a normally open momentary switch in parallel with R2 (Figure 3). When the switch is closed, the voltage on RESET IN goes to zero, initiating a reset. Similar to the MAX6746/ MAX6747 manual reset, reset remains asserted while the voltage at RESET IN is zero and for the reset timeout period after the switch is opened.
Figure 3. Adding an External Manual Reset Function to the MAX6748-MAX6751
where VMON_TH is the desired reset threshold voltage and VTH is the reset input threshold (1.235V). Resistors R1 and R2 can have very high values to minimize current consumption due to low leakage currents. Set R2 to some conveniently high value (500k, for example) and calculate R1 based on the desired reset threshold voltage, using the following formula: R1 = R2 x (VMON_TH/VRESET IN - 1) () The MAX6748 and MAX6749 do not monitor VCC supply voltage, therefore, VCC must be greater than 1.5V to
VCC WDI OV VCC RESET OV NORMAL MODE (WDS = GND) tWD tRP
Figure 4a. Watchdog Timing Diagram, WDS = GND
8
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P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746-MAX6753
VCC WDI OV VCC RESET OV EXTENDED MODE (WDS = VCC) tWD x 128 tRP
Figure 4b. Watchdog Timing Diagram, WDS = VCC
Watchdog Timer
MAX6746-MAX6751 The watchdog's circuit monitors the P's activity. It the P does not toggle the watchdog input (WDI) within tWD (user-selected), RESET asserts for the reset timeout period. The internal watchdog timer is cleared by any event that asserts RESET, by a falling transition at WDI (which can detect pulses as short as 300ns) or by a transition at WDS. The watchdog timer remains cleared while reset is asserted; as soon as reset is released, the timer starts counting. The MAX6746-MAX6751 feature two modes of watchdog operation: normal mode and extended mode. In normal mode (Figure 4a), the watchdog timeout period is determined by the value of the capacitor connected between SWT and ground. In extended mode (Figure 4b), the watchdog timeout period is multiplied by 128. For example, in extended mode, a 0.1F capacitor gives a watchdog timeout period of 65s (see the Extended-Mode Watchdog Timeout Period vs. CSWT graph in the Typical Operating Characteristics). MAX6752/MAX6753 The MAX6752 and MAX6753 have a windowed watchdog timer that asserts RESET for the adjusted reset timeout period when the watchdog recognizes a fast watchdog fault (tWDI < tWD1), or a slow watchdog fault (period > tWD2). The reset timeout period is adjusted independently of the watchdog timeout period. The slow watchdog period, tWD2 is calculated as follows: tWD2 = 0.65 x 109 x CSWT with tWD2 in seconds and CSWT in Farads. The fast watchdog period, tWD1, is selectable as a ratio from the slow watchdog fault period (tWD2). Select the fast watchdog period by pinstrapping SET0 and SET1, where HIGH is VCC and LOW is GND. Table 1 illus-
Table 1. Min/MAX Watchdog Setting
SET0 LOW LOW HIGH HIGH SET1 LOW HIGH LOW HIGH RATIO 8 16 Watchdog Disabled 64
trates the SET0 and SET1 configuration for the 8, 16, and 64 window ratio ( tWD2/tWD1). For example, if CSWT is 1500pF, and SET0 and SET1 are low, then tWD2 is 975ms (typ) and tWD1 is 122ms (typ). RESET asserts if the watchdog input has two falling edges too close to each other (faster than tWD1) (Figure 5a) or falling edges that are too far apart (slower than tWD2) (Figure 5b). Normal watchdog operation is displayed in (Figure 5c). The internal watchdog timer is cleared when a WDI falling edge is detected within the valid watchdog window or when RESET is deasserted. All WDI inputs are ignored while RESET is asserted. The watchdog timer begins to count after RESET is deasserted. The watchdog timer clears and begins to count after a valid WDI falling logic input. WDI falling transitions within periods shorter than tWD1 or longer than tWD2 force RESET to assert low for the reset timeout period. WDI falling transitions within the tWD1 and t WD2 window do not assert RESET. WDI transitions between t WD1(min) and t WD1(max) or t WD2(min) and tWD2(max) are not guaranteed to assert or deassert the RESET. To guarantee that the window watchdog does not assert the RESET, strobe WDI between tWD1(max) and tWD2(min). The watchdog timer is cleared when RESET is asserted or after a falling transition on WDI or after a state change on SET0 or SET1. Disable the watchdog timer by connecting SET0 high and SET1 low.
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P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746-MAX6753
tWDI < tWD1 (MIN) 5V 3.3V
VCC WDI RESET
MAX6747 MAX6749 MAX6451 MAX6753
(a) FAST FAULT RESET N tWDI > tWD2 (MAX) GND
100k VCC
RESET
P
GND
WDI RESET
Figure 6. Interfacing to Other Voltage Levels
(b) SLOW FAULT tWD1 (MAX) < tWDI < tWD2 (MIN)
normal mode operation, calculate the watchdog timeout capacitor as follows: CSWT = tWD/(5.06 x 106), with tRP in seconds and CSRT in Farads. For the MAX6752 and MAX6753 windowed watchdog function, calculate the slow watchdog period, tWD2 as follows: tWD2 = 0.65 x 109 x CSWT CSRT and CSWT must be a low-leakage (<10nA) type capacitor. Ceramic capacitors are recommended.
WDI RESET
(c) NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH)
Transient Immunity
Figure 5. MAX6752/MAX6753 Window Watchdog Diagram
Applications Information
Selecting Reset/Watchdog Timeout Capacitor
The reset timeout period is adjustable to accommodate a variety of P applications. Adjust the reset timeout period (tRP) by connecting a capacitor (CSRT) between SRT and ground. Calculate the reset timeout capacitor as folllows: CSRT = tRP / (5.06 x 106), with tRP in seconds and CSRT in Farads. The watchdog timeout period is adjustable to accommodate a variety of P applications. With this feature, the watchdog timeout can be optimized for software execution. The programmer can determine how often the watchdog timer should be serviced. Adjust the watchdog timeout period (tWD) by connecting a specific value capacitor (CSWT) between SWT and GND. For
10
In addition to issuing a reset to the P during power-up, power-down, and brownout conditions, these supervisors are relatively immune to short-duration supply transients (glitches). The Maximum Transient Duration vs. Reset Threshold Overdrive graph in the Typical Operating Characteristics shows this relationship. The area below the curves of the graph is the region in which these devices typically do not generate a reset pulse. This graph was generated using a falling pulse applied to VCC , starting above the actual reset threshold (VTH) and ending below it by the magnitude indicated (reset-threshold overdrive). As the magnitude of the transient increases (farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts 50s or less does not cause a reset pulse to be issued.
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P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay
Interfacing to Other Voltages for Logic Compatibility
The open-drain RESET output can be used to interface to a P with other logic levels. As shown in Figure 6, the open-drain output can be connected to voltages from 0 to 6V. Generally, the pullup resistor connected to the RESET connects to the supply voltage that is being monitored at the IC's VCC pin. However, some systems can use the open-drain output to level-shift from the monitored supply to reset circuitry powered by some other supply. Keep in mind that as the supervisor's VCC decreases towards 1V, so does the IC's ability to sink current at RESET. Also, with any pullup resistor, RESET is pulled high as VCC decays toward zero. The voltage where this occurs depends on the pullup resistor value and the voltage to which it is connected.
Ensuring a Valid RESET Down to VCC = 0V (Push-Pull RESET)
When VCC falls below 1V, RESET current sinking capabilities decline drastically. The high-impedance CMOSlogic inputs connected to RESET can drift to undetermined voltages. This presents no problems in most applications, since most Ps and other circuitry do not operate with VCC below 1V. In those applications where RESET must be valid down to 0V, add a pulldown resistor between RESET and GND for the MAX6746/MAX6748/MAX6750/MAX6752 push/pull outputs. The resistor sinks any stray leakage currents, holding RESET low (Figure 7). The value of the pulldown resistor is not critical; 100k is large enough not to load RESET and small enough to pull RESET to ground. The external pulldown can not be used with the open-drain reset outputs.
MAX6746-MAX6753
VCC VCC
MAX6746 MAX6748 MAX6450 MAX6752
RESET 100k GND
Figure 7. Ensuring RESET Valid to VCC = 0
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P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746-MAX6753
Table 2. Reset Threshold Voltage Suffix (TA = -40C to +125C)
SUFFIX 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MIN 4.900 4.802 4.704 4.606 4.533 4.410 4.288 4.214 4.116 4.018 3.920 3.822 3.724 3.626 3.528 3.430 3.332 3.234 3.136 3.014 2.940 2.867 2.744 2.646 2.573 2.450 2.352 2.267 2.144 2.058 1.960 1.862 1.764 1.632 1.544 TYP 5.000 4.900 4.800 4.700 4.625 4.500 4.375 4.300 4.200 4.100 4.000 3.900 3.800 3.700 3.600 3.500 3.400 3.300 3.200 3.075 3.000 2.925 2.800 2.700 2.625 2.500 2.400 2.313 2.188 2.100 2.000 1.900 1.800 1.665 1.575 MAX 5.100 4.998 4.896 4.794 4.718 4.590 4.463 4.386 4.284 4.182 4.080 3.978 3.876 3.774 3.672 3.570 3.468 3.366 3.264 3.137 3.060 2.984 2.856 2.754 2.678 2.550 2.448 2.359 2.232 2.142 2.040 1.938 1.836 1.698 1.607
Table 3. Standard Version Table
PART MAX6746KA16 MAX6746KA23 MAX6746KA26 MAX6746KA29 MAX6746KA46 MAX6747KA16 MAX6747KA23 MAX6747KA26 MAX6747KA29 MAX6747KA46 MAX6748KA MAX6749KA MAX6750KA16 MAX6750KA23 MAX6750KA26 MAX6750KA29 MAX6750KA46 MAX6751KA16 MAX6751KA23 MAX6751KA26 MAX6751KA29 MAX6751KA46 MAX6752KA16 MAX6752KA23 MAX6752KA26 MAX6752KA29 MAX6752KA46 MAX6753KA16 MAX6753KA23 MAX6753KA26 MAX6753KA29 MAX6753KA46 TOP MARK AEDI AEDJ AEDK AALN AEDL AALO AEDM AEDN AEDO AEDP AALP AALQ AEDQ AALR AEDR AEDS AEDT AEDU AEDV AEDW AEDX AEDY AEDZ AEEA AALT AEEB AEEC AEED AEEE AEEF AEEG AEEH
Note: Standard versions are shown in bold. There is a 2500piece minimum order increment for standard versions. Sample stock is typically held on standard versions only. Nonstandard versions require a minimum order increment of 10,000 pieces. Contact factory for availability.
12
______________________________________________________________________________________
P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746-MAX6753
Selector Guide
PART MAX6746 MAX6747 MAX6748 MAX6749 MAX6750 MAX6751 MAX6752 MAX6753 FIXED VCC RESET THRESHOLD * * -- -- * * * * ADJUSTABLE RESET THRESHOLD -- -- * * * * -- -- STANDARD WATCHDOG TIMER * * * * * * -- -- MIN/MAX WATCHDOG TIMER -- -- -- -- -- -- * * PUSH/ PULL RESET * -- * -- * -- * -- OPEN-DRAIN RESET -- * -- * -- * -- * MANUAL RESET INPUT * * -- -- -- -- -- --
Typical Operating Circuit
VIN MAX6749 MAX4751 VCC R1
Pin Configurations (continued)
TOP VIEW
SET0 1 SWT 2
8 7
VCC RESET WDI SET1
RESET IN
VCC P
SRT
3
MAX6752 MAX6753
6 5
R2 GND
MAX6748 MAX6749 MAX6750 MAX6751
GND 4
RESET
RESET
SOT23-8
CSRT CSWT
SRT WDI SWT WDS I/O
Chip Information
TRANSISTOR COUNT: 1100 PROCESS: BiCMOS
WDS = 0 FOR NORMAL MODE WDS = VCC FOR EXTENDED MODE
______________________________________________________________________________________
13
P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746-MAX6753
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOT23, 8L .EPS
REV.
SEE DETAIL "A" b
C L
e
SYMBOL A A1 A2 b C D E E1 L L2 e e1
MIN 0.90 0.00 0.90 0.28 0.09 2.80 2.60 1.50 0.30
MAX 1.45 0.15 1.30 0.45 0.20 3.00 3.00 1.75 0.60 0.25 BSC. 0.65 BSC. 1.95 REF.
C L
E
C L
E1
PIN 1 I.D. DOT (SEE NOTE 6) e1 D C
C L
0
0
8
L2 A A2 A1
SEATING PLANE C
GAUGE PLANE
L
0
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. FOOT LENGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF HEEL OF THE LEAD PARALLEL TO SEATING PLANE C. 3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR. 4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING. 5. COPLANARITY 4 MILS. MAX. 6. PIN 1 I.D. DOT IS 0.3 MM MIN. LOCATED ABOVE PIN 1. 7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD BETWEEN 0.08mm AND 0.15mm FROM LEAD TIP. 8. MEETS JEDEC MO178.
PROPRIETARY INFORMATION TITLE:
DETAIL "A"
PACKAGE OUTLINE, SOT-23, 8L BODY
APPROVAL DOCUMENT CONTROL NO.
21-0078
1 1
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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